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San José

Soc Design Engineer

14-09-2024 - Intel - Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete ...
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Heredia

Middleware Engineer

14-09-2024 - Ntt Data - **Req ID**: 257255 We are currently seeking a Middleware Engineer to join our team in Heredia, Heredia (CR-H), Costa Rica (CR). **Position overview** **Position's General ...
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Heredia

Data Engineer

14-09-2024 - Infotree Global Solutions - Hybrid position, one day a week you will need to go to the office - Create data processing code needed to feed data-marts out of current warehouse (i.e. data ...
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San José

Customer Support Engineer

14-09-2024 - Appvance.Ai - **About the Role**: To further accelerate, Appvance is seeking an experienced Customer Support Engineer to join our Customer Success Team. You will be responsible for ...
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San José

Quality Assurance Automation Engineer

14-09-2024 - Moon Hi - As a QA Automation Engineer, you will be responsible for designing, developing, and maintaining automated testing solutions to ensure our applications perform at high quality ...
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San José

Analog Design Engineer

14-09-2024 - Intel - We are looking for a highly motivated analog design engineer to join the Chipsets Silicon Group (CSG) Circuits team for Intel's next generation of chipsets/SOC. As part of the ...
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Heredia

Managed Monitoring Services L2 Engineer

14-09-2024 - Hewlett Packard - **Job Summary** - This role is responsible for effectively resolving moderate technical issues involving hardware and software through interactions with internal and ...
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San José

Staff Engineer, Cloud

14-09-2024 - Pfizer - ROLE SUMMARY The Digital Hosting Solutions (DHS) team represents the Digital Center of Excellence (CoE) for cloud infrastructure capabilities, providing foundational public and ...
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San José

Physical Design Static Timing Analysis Engineer

14-09-2024 - Intel - Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and ...
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